KIIT Deemed to be University SDT Quiz (Activity-5) Topic: Module-4 and Module-6 âąī¸ 20:00 đ 10 Questions 1 Registration & Summary âšī¸ Quiz Summary Main Topic Topic: Module-4 and Module-6 Questions 10 Items Time Limit 20 Minutes Negative Marking â None Name * Roll Number * Ready to begin? The timer starts immediately. đ Continue & Start Test 2 Quiz Questions Q1. When performing an experiment with 4 factors, each at 2 levels, a half-fractional factorial design (2 to the power of 4-1) requires how many experimental runs? 4 runs 8 runs 32 runs 16 runs Q2. In a standard 3D NAND process flow, what is one of the most difficult and critical unit processes? High aspect ratio deep trench/hole etching Low temperature baking Aluminum wire bonding Chemical mechanical polishing of the back side Q3. In statistical analysis, what is the primary purpose of an Analysis of Variance (ANOVA) test? To find the correlation coefficient between two variables To test if the means of three or more independent groups are significantly different To compare the variances of two independent samples To predict a future outcome based on past data Q4. What is the theoretical minimum limit for Subthreshold Swing in a standard MOSFET operating at room temperature (300 K)? 10 millivolts per decade 60 millivolts per decade 100 millivolts per decade 0 millivolts per decade Q5. Response Surface Methodology (RSM) is highly useful in semiconductor process engineering primarily for: Modeling curvature and finding the optimal peak or valley of a process window Eliminating the need for statistical software Identifying which machine is broken Plotting control charts Q6. Why are silicide materials (like NiSi or TiSi2) formed on top of the silicon source, drain, and gate regions? To increase the bandgap of the silicon To serve as a light-emitting layer To significantly reduce the contact resistance between the semiconductor and the metal interconnect vias To act as a protective barrier against moisture Q7. What is the primary advantage of the gate-last (Replacement Metal Gate) integration scheme over the gate-first scheme? It completely eliminates the need for CMP It uses cheaper metals It prevents the delicate high-k material and metal gate from being damaged by the high temperatures of source/drain activation anneals It requires fewer lithography steps Q8. What is the main trade-off or disadvantage of using a fractional factorial DOE instead of a full factorial DOE? Main effects become confounded or aliased with higher-order interactions It only tests one factor at a time It cannot be used in semiconductor manufacturing It requires more experimental runs Q9. In semiconductor manufacturing, what is a Design Rule Manual (DRM)? A list of prices for different silicon wafers A document detailing geometric constraints and spacing requirements to ensure the drawn layout can actually be manufactured A manual for repairing photolithography tools A software code that tests the chips Q10. In semiconductor device physics, Subthreshold Swing (SS) is a critical parameter. What does a lower Subthreshold Swing value indicate? The transistor turns on more sharply and efficiently, requiring less gate voltage to increase the drain current The transistor is suffering from electromigration The transistor requires more voltage to turn on The transistor has higher resistance đ¯ Complete My Submission
