KIIT Deemed to be University SDT Quiz (Activity-5) Topic: Module-4 and Module-6 âąī¸ 20:00 đ 10 Questions 1 Registration & Summary âšī¸ Quiz Summary Main Topic Topic: Module-4 and Module-6 Questions 10 Items Time Limit 20 Minutes Negative Marking â None Name * Roll Number * Ready to begin? The timer starts immediately. đ Continue & Start Test 2 Quiz Questions Q1. In SPC, what does Cp and Cpk measure in a manufacturing environment? Process capability, assessing how well the natural variation of a process fits within the customer specification limits The chemical purity of the water used in the fab The speed at which wafers move through the fab The amount of power consumed by a lithography tool Q2. What is the main disadvantage of the LOCOS (Local Oxidation of Silicon) isolation technique that led to its replacement in advanced nodes? It requires extremely high pressures The formation of a bird's beak oxide encroachment It is too expensive to perform It uses toxic chemicals Q3. In a Dual Damascene process, which two structural features are filled with copper simultaneously in a single deposition step? The source and the drain The N-well and the P-well The gate and the substrate The vertical via and the overlying horizontal metal trench Q4. On a standard SPC control chart, which of the following is considered an out-of-control signal requiring engineering intervention? A single point falling outside the 3-sigma control limits A normal bell-curve distribution of data Data points fluctuating randomly around the mean Several points falling within the 1-sigma zone Q5. What does the term salicide mean in the context of semiconductor manufacturing? Safe and Low-cost Silicide Sacrificial Silicide Silicon and Aluminum compound Self-Aligned Silicide Q6. What is the main function of the Lightly Doped Drain (LDD) region in a MOSFET? To serve as the primary contact point for interconnects To increase the gate capacitance To reduce the peak electric field near the drain, thereby minimizing hot-carrier injection To increase the total current of the transistor Q7. What is the main objective of using low-k dielectrics as Inter-Layer Dielectrics (ILD) between metal interconnects? To increase the breakdown voltage of the transistors To reduce the parasitic capacitance between adjacent metal wires, thereby reducing RC delay and crosstalk To increase the heat generation of the chip To provide structural rigidity Q8. In a CMOS process, what is the purpose of forming a well (e.g., an n-well or p-well)? To connect the transistor to the power grid To store cooling fluid To provide a deep, localized region of specific doping to act as the substrate for a specific type of transistor To trap stray light particles Q9. When conducting a hypothesis test, a Z-test is most appropriate to use instead of a T-test when: The sample size is very small (less than 30) The data is highly skewed The population standard deviation is known You are comparing more than three groups Q10. How does a FinFET architecture fundamentally improve upon a traditional planar transistor? It operates without a gate terminal The gate wraps around three sides of the channel for superior electrostatic control It uses less silicon material It eliminates the need for interconnects đ¯ Complete My Submission
